The Tachyon Instruction Emulator provides an execution environment that is highly compatible with the IBM System/390 and z/Architecture application programming facilities. These facilities are described in detail in the IBM Enterprise Systems Architecture/390 Principles of Operation and IBM z/Architecture Principles of Operation. Some system-level such as Machine Check Handling and the Channel Subsystem are not emulated. The facilities which are provided are:
The Tachyon Instruction Emulator provides the full set of general, access, control and floating point registers. Within the debugger, you can display and alter these registers. The general and floating point registers function as described in the ESA/390 Principles of Operation manual. When the emulator runs in architecture level 2 the register function as described in IBM z/Architecture Principles of Operation and the general and control registers are 64 bits in length.
This version of the Tachyon Instruction Emulator supports only one address space and no data spaces and therefore the PSW cannot be usefully set to access-register mode. However, LAM, STAM, LAE, SAR and other instructions that explicitly reference the access registers function correctly.
When the emulator runs in architecture level 0, any attempt to set the PSW to access register mode will cause a Specification or Special Operation exception. When the emulator run in architecture level 1 or 2 and the PSW is in access register mode, any referenced ALET value must be 0, 1 or 2 (primary, secondary or home space).The Tachyon Instruction Emulator uses the contents of some of the control registers in a similar manner to the way they are used by the IBM System/390. The contents of control registers 0, 5 and 15 are of particular significance. The Tachyon Operating System initializes other control registers to reasonable values. For instance, the Address Space Number (ASN) is set to 1. In all cases storage addresses are virtual since the Tachyon Instruction Emulator does not support the concepts of real or absolute storage.
The External Interrupt Mask, the PSW key, PSW Format, Wait State and Problem State bits, the Address Space Control bits, the Condition Code, the Program Mask, the Addressing Mode and the Instruction Address fields are significant to the Tachyon Operating System. Within the debugger, you can display and alter the PSW.
The Time Of Day Clock is normally set consistently with your workstation’s clock. The TOD clock value can be offset from your workstation’s clock through the LOADxx.ini CLOCK parameter or the j390 -clock parameter. Because the workstation clock does not typically have the same resolution as the System/390 clock, the Tachyon Instruction Emulator will increment the microsecond counter each time the TOD clock is accessed within a single workstation time interval.
The Tachyon 390 Emulator supports one complete System/390 virtual address space. Both 24-bit and 31-bit address modes are supported. When the emulator runs in architecture level 2, the 64-bit addressing mode is also supported. Real and absolute storage and data spaces are not supported. All of the allocated System/390 virtual storage is also allocated from your workstation’s virtual storage. Although the full address space is supported, your workstation operating system probably does not have enough memory to allow the address space to be fully allocated.
This release of the Tachyon Instruction Emulator supports a simpler storage protection mechanism than the full System/390 facility. Instead of using the entire storage key in the PSW, the Tachyon Instruction Emulator uses only the high bit (bit 8 of the PSW). If the PSW key is less than 8 (if bit 8 of the PSW is zero), all storage may be accessed and modified. If the PSW key is 8 or greater, some storage cannot be accessed and other storage cannot be modified. Low Address Protection and Page Protection are supported.
Some of the fields in the first page (4 kilobytes) of storage are used by the Tachyon Instruction Emulator. These fields include the old and new Supervisor Call, Program Check and External Interrupt PSWs and the associated status areas.
The Tachyon Instruction Emulator supports both basic and stacking Program Calls. Since the Tachyon Instruction Emulator only supports one address space, space switching Program Calls are not supported. The Linkage Table and the Linkage Stack are fully supported as described in detail in ESA/390 Principles of Operation and the first edition of IBM z/Architecture Principles of Operation.
When the Tachyon Instruction Emulator runs in architecture level 0 or 1, it supports the instructions described in the General Instructions, Decimal Instructions, Floating Point Overview and Support Instructions Hexadecimal Floating Point Instructions and Binary Floating Point Instructions chapters of the ninth edition of the IBM Enterprise Systems Architecture/390 Principles of Operation (order number SA22-7201-8). When the emulator runs in architecture level 2, it supports the instructions in these same chapters of the fifth edition of IBM z/Architecture Principles of Operation (order number SA22-7832-4). In addition, the emulator supports the instructions described in IBM System/370 Mathematical Assists (order number SA22-7094-1). The CMPSC, KIMD, KLMD, KM, KMAC and KMC general instructions and the MAY, MAYR, MAYH, MAYHR, MAYL, MAYLR, MY, MYR, MYH, MYHR, MYL and MYLR hexadecimal floating point instructions are not supported.
The Tachyon Instruction Emulator also supports the following instructions described in the Control Instructions chapter of the ESA/390 Principles of Operation manual: BAKR, EPAR, ESAR, EREG, ESTA, IAC, IPK, IVSK, LCTL, LPSW, MSTA, MVPG, PC, PR, PT, RP, SAC, SACF, SPKA, SSM, STCTL, STNSM, STOSM, TAR and TPROT. When the emulator runs in architecture level 2, these instructions plus EREGG, ESEA, LCTLG, LPSWE, STCTG and STFL are supported as described in the IBM z/Architecture Principles of Operation.
Even when the emulator runs in architecture level 0 or 1, it supports the following z/Architecture-only instructions as described in the IBM z/Architecture Principles of Operation: CU14, CU24, CU41, CU42, IILH, IILL, NILH, NILL, OILH, OILL, SRSTU, STCKF, STFLE and TRTR.